Enter Synthesizer Inputs
Solve mode derives divider values for a requested output. Evaluate mode checks an existing N and fractional setup against your target and spacing plan.
Example Data Table
| Reference (MHz) | Doubler | R | Integer N | Fraction | Output Divider | PFD (MHz) | VCO (MHz) | RF Output (MHz) |
|---|---|---|---|---|---|---|---|---|
| 10 | On | 1 | 120 | 1/5 | 4 | 20 | 2404 | 601 |
| 25 | Off | 5 | 800 | 1/4 | 8 | 5 | 4001.25 | 500.15625 |
| 19.2 | Off | 1 | 130 | 3/8 | 2 | 19.2 | 2503.2 | 1251.6 |
| 100 | Off | 10 | 290 | 7/20 | 1 | 10 | 2903.5 | 2903.5 |
Formula Used
This calculator follows a practical fractional-N PLL synthesizer model. It estimates phase detector frequency, total divider ratio, VCO frequency, RF output, step size, and approximate lock behavior.
Lock time is a simplified estimate. Real hardware behavior also depends on loop filter design, charge pump settings, VCO gain, damping, and noise sources.
How to Use This Calculator
- Choose solve mode to derive divider values from a target frequency, or evaluate mode to inspect an existing divider configuration.
- Enter the reference source frequency and the reference divider R. Enable the doubler only when your synthesizer path actually uses it.
- Set the fractional denominator and output divider. These strongly influence channel spacing and achievable frequency resolution.
- Enter desired channel spacing and loop bandwidth to assess resolution fit and estimate settling behavior.
- Press calculate. Review the result summary, metric table, and plot to confirm divider quality, error size, and tuning trend.
- Use the CSV button for tabular export and the PDF button for a shareable engineering snapshot.
Frequently Asked Questions
1) What does this calculator estimate?
It estimates key PLL synthesizer values, including PFD frequency, total N ratio, VCO output, final RF output, frequency step size, target error, and approximate lock time.
2) Why is the output divider important?
The output divider scales the VCO frequency down to the required RF output. It also reduces the RF step size, which can help achieve finer channel spacing.
3) What is the difference between solve and evaluate mode?
Solve mode calculates divider values for a requested output frequency. Evaluate mode checks a divider setup you already have and reports the resulting output, error, and resolution.
4) Does the lock time reflect real hardware exactly?
No. It is only a quick engineering estimate. Real lock time changes with loop filter topology, damping, VCO gain, charge pump current, phase noise, and silicon behavior.
5) Why do I see a small frequency error in solve mode?
Fractional synthesizers use discrete steps. If your target falls between available steps, the calculator rounds to the closest realizable frequency based on your modulus and divider settings.
6) How can I improve tuning resolution?
Increase the fractional denominator, reduce the PFD frequency carefully, or use a larger output divider when architecture allows it. Each change affects noise, settling, and spur behavior.
7) What does steps per channel mean?
It shows how many synthesizer increments fit inside your requested channel spacing. Values close to whole numbers indicate cleaner alignment between channel plan and available frequency steps.
8) Can I use this for integer-N designs?
Yes. Set the fractional numerator to zero and use any denominator value of at least one. The calculator then behaves like an integer-N evaluation tool.