Formula used
This calculator uses a common integer-N PLL frequency plan.
- fPFD = fREF / R (phase detector frequency)
- fVCO = fPFD × N (VCO frequency)
- fOUT = fVCO / M (output frequency)
- Gain = fOUT / fREF = N / (R × M) (net multiplier)
How to use this calculator
- Enter your reference frequency and select its unit.
- Set divider values R, N, and M from your registers.
- Provide maximum PFD frequency and valid VCO range.
- Press Calculate to show results above the form.
- Review flags, then export CSV or PDF if needed.
Example data table
| fREF | R | N | M | fPFD | fVCO | fOUT |
|---|---|---|---|---|---|---|
| 10 MHz | 1 | 24 | 2 | 10 MHz | 240 MHz | 120 MHz |
| 25 MHz | 5 | 80 | 4 | 5 MHz | 400 MHz | 100 MHz |
| 40 MHz | 2 | 60 | 3 | 20 MHz | 1200 MHz | 400 MHz |
Notes and cautions
- Confirm limits and ranges from your device datasheet.
- Fractional-N PLLs add terms not modeled here.
- Loop filter values set stability and noise behavior.
- Spur performance depends on architecture and layout.
Divider planning and frequency translation
A PLL frequency plan begins with the reference input and the divider chain. The phase detector frequency equals the reference divided by R, and the VCO frequency equals that PFD rate multiplied by N. Choosing R and N is a practical tradeoff between resolution and speed. A higher PFD generally improves loop bandwidth options, while an excessive N often increases in-band noise contribution and may amplify sensitivity to reference disturbances.
PFD limit checks for reliable operation
Datasheets usually specify a maximum phase-frequency detector or charge pump comparison rate. When fPFD exceeds that value, internal timing margins shrink and spurious behavior can rise. This calculator compares your computed fPFD against the limit you enter, then flags the result. Keeping fPFD comfortably below the ceiling also helps with temperature drift and process variation across lots.
VCO window selection and coverage
Most integrated PLLs operate a VCO inside a defined tuning range. If your calculated fVCO sits outside that window, the loop cannot lock without changing dividers or selecting another VCO band. Entering minimum and maximum VCO frequencies lets you validate feasibility quickly. In practice, designers also leave guard band at both ends to accommodate supply variation and component tolerances.
Multiplier gain and output divider effects
The delivered output equals fVCO divided by M, so the output divider is an efficient way to reach lower clocks while maintaining a high VCO. Net multiplication from reference to output equals N divided by R times M. If you must hit an exact target, adjust N for coarse movement, then use R or M to keep fPFD and fVCO within limits. Balanced settings reduce stress on any single block.
Documentation exports for design reviews
Engineering teams often need repeatable records of divider choices and computed frequencies. The built-in CSV export captures the result table for spreadsheets, while the PDF export produces a shareable snapshot for approvals and test reports. Using consistent exports accelerates peer review, helps correlate lab measurements with planned values, and reduces transcription errors when updating register maps or configuration scripts. It supports traceability when comparing simulated phase noise, measured spurs, and field performance over time.
FAQs
What is the main output equation used here?
The calculator uses an integer-N plan: fPFD = fREF/R, fVCO = fPFD×N, and fOUT = fVCO/M. Net gain is N/(R×M). This matches many clock generator and synthesizer divider chains.
Can I use this for fractional-N PLLs?
It will still compute the basic frequencies, but fractional modulators add additional terms such as fractional numerator/denominator, sigma-delta behavior, and spur patterns. Use this tool for quick planning, then confirm with the device’s fractional model.
Why is the PFD limit important?
Running the phase detector above its rated comparison frequency can reduce timing margin, distort charge pump switching, and worsen spurs. Staying within the limit improves robustness across temperature, voltage, and manufacturing variation.
What if the VCO result is outside the range?
If fVCO is below the minimum or above the maximum, the loop usually cannot lock in that band. Change N and/or R, select a different VCO band if available, or adjust the output divider M while keeping fPFD legal.
How should I choose R, N, and M?
Start with the desired fOUT and a preferred fPFD that is safely under the limit. Choose N so fVCO lands near the center of the VCO range, then pick M to reach the final output. Re-check constraints and iterate.
What do the CSV and PDF exports include?
Exports capture the results table shown after calculation, including your input values and computed fPFD, fVCO, fOUT, and gain. CSV is convenient for spreadsheets, while PDF is helpful for reviews, approvals, and test documentation.