Calculator inputs
Example data table
| Clock | Target | Timer | Mode | Prescaler | ARR | Result |
|---|---|---|---|---|---|---|
| 72 MHz | 1 kHz | 16-bit | Timebase | 72 (reg 71) | 999 | 1.000 kHz, ~0% error |
| 16 MHz | 1 ms | 16-bit | Timebase | 16 (reg 15) | 999 | 1.000 ms, ~0% error |
| 48 MHz | 20 kHz, 25% | 16-bit | PWM | 1 (reg 0) | 2399 | 20.000 kHz; CCR ~600 |
Formula used
A basic up-counter timer divides the input clock by a prescaler, then counts to an auto-reload limit.
- f_tick = f_clk / Prescaler
- Period = (ARR + 1) / f_tick
- Frequency = f_clk / (Prescaler × (ARR + 1))
For PWM, the period uses the same relationship. Duty is set by a compare value:
- CCR ≈ (ARR + 1) × Duty% (clamped into the valid range)
- Many devices store the prescaler register as Prescaler − 1.
How to use this calculator
- Enter the timer clock that increments the counter.
- Select a target frequency or period for the update event.
- Choose timer size so ARR fits your hardware.
- Pick a prescaler strategy matching available divider options.
- Optionally lock prescaler or ARR to meet constraints.
- Press Submit to see recommended values and alternatives.
- Download CSV or PDF to document your configuration.
Prescaler selection logic
Prescalers divide the timer clock so the counter tick becomes practical. This calculator can scan any integer range, powers of two, common sets, or a custom list. Use a narrow range when the silicon only supports specific dividers. A wider search improves accuracy but may add configurations you cannot program. The tool reports both the human prescaler and the register value, typically prescaler minus one.
Reload value and resolution
The auto‑reload register (ARR) sets the period in counter ticks. For an N‑bit timer, ARR must stay between 0 and 2^N − 1, which defines the longest reachable period at a given tick rate. Higher ARR values also improve duty and phase resolution because each count represents a smaller fraction of the cycle. When targeting slow events, increasing prescaler is usually safer than overflowing ARR.
Frequency and period targeting
You may target frequency or period; both map to the same total counts: counts = f_clk / f_out, or counts = f_clk × T_out. The calculator computes the nearest ARR for each prescaler using a chosen rounding preference, then evaluates error in absolute units and percent. Review the reported actual frequency and actual period together to ensure the result aligns with system requirements such as interrupt latency budgets.
PWM duty considerations
In PWM mode, period comes from prescaler and ARR, while duty comes from the compare value (CCR). The calculator estimates CCR from (ARR+1) × duty%, then clamps it to valid limits. It also reports the duty step size, approximately 100/(ARR+1) percent, which tells you how finely you can adjust pulse width. If your duty resolution is poor, reduce prescaler or increase ARR within range.
Validation and documentation workflow
After selecting a candidate, confirm the timer clock source and upstream bus dividers in your schematic and clock tree. Then validate with a scope or logic analyzer, considering oscillator tolerance and temperature drift. For safety‑critical scheduling, prefer configurations with low percent error and stable tick rates. Export CSV for design reviews and generate a PDF report for firmware documentation, test plans, and compliance evidence. Keep top candidates nearby when tuning low-power modes or compensating for clock changes during runtime.
FAQs
What input clock should I use for the timer?
Use the clock that actually feeds the timer counter after all bus dividers and clock muxes. Many MCUs provide different timer clocks on different buses. Confirm the effective frequency in your clock tree tool or reference manual before calculating.
Why does the prescaler register differ from the prescaler value?
Many timer peripherals store PSC as prescaler minus one. If the calculator recommends prescaler 72, you typically program PSC to 71. Always verify the exact convention for your specific timer instance.
How accurate are the results when the target is not exactly reachable?
The tool searches feasible PSC and ARR pairs and reports the closest matches. Accuracy is limited by integer division and timer bit width. Choose the candidate with the smallest percent error that also satisfies duty and jitter constraints.
When should I lock prescaler or ARR?
Lock prescaler when hardware only supports specific divider steps or when you must keep a fixed tick for multiple channels. Lock ARR when you need a precise counter length and can adjust only the prescaler to hit timing goals.
How is PWM duty computed in this calculator?
It computes CCR from (ARR+1) times duty percent, then clamps it within 0 to ARR. The duty step indicator shows your minimum adjustment granularity, which improves as ARR increases.
Do CSV and PDF exports include all candidates?
Exports include the saved calculation inputs plus the displayed top candidates list. Increase the “Show top candidates” value before exporting if you need a broader comparison set for reviews or regression documentation.