Cadence MOSFET Output Resistance Calculator

Advanced Simulation Parameters

Drain Current ($I_D$ in mA)

Example: 1.0 mA

Early Voltage ($V_A$ in V)

Example: 25.0 V

Modulation Parameter ($\lambda$ in V$^{-1}$)

Example: 0.04 V⁻¹

Drain-Source Voltage ($V_{DS}$ in V)

Example: 1.8 V

Overdrive Voltage ($V_{OV}$ in V)

Example: 0.3 V

Channel Length ($L$ in $\mu$m)

Example: 0.18 $\mu$m

Channel Width ($W$ in $\mu$m)

Example: 10.0 $\mu$m

Transconductance ($K_p$ in $\mu$A/V$^2$)

Example: 120.0 $\mu$A/V²

DIBL Coefficient ($\eta$)

Example: 0.05

Temperature ($^\circ$C)

Formula Used

In analog integrated circuit design within environments like Cadence Virtuoso, the MOSFET output resistance ($r_o$) in the saturation region is primarily determined by channel length modulation and Early voltage effects:

Base Output Resistance: $$r_o = \frac{V_A}{I_D}$$ or $$r_o = \frac{1}{\lambda I_D}$$

Channel Length Modulation Parameter ($\lambda$): In short-channel devices, $\lambda$ scales inversely with channel length $L$.

DIBL Correction: Drain-Induced Barrier Lowering modifies the effective output resistance: $$r_{o,\text{eff}} = r_o \times (1 - \eta \cdot V_{DS})$$

How to Use This Calculator

Review the default pre-filled example inputs for a standard 0.18$\mu$m CMOS technology node.

Modify parameters such as Drain Current ($I_D$), Early Voltage ($V_A$), and Channel Length ($L$) according to your Cadence schematic or model cards.

Click the Calculate Output Resistance button to execute the simulation computation.

Analyze the resulting output resistance ($r_o$), output conductance ($g_{ds}$), and effective lambda displayed prominently above the form.

Understanding Cadence MOSFET Output Resistance

Accurately predicting MOSFET output resistance is critical for designing high-gain analog amplifiers, current mirrors, and complex analog-to-digital converters in Cadence EDA software. In modern sub-micron processes, short-channel effects like velocity saturation and drain-induced barrier lowering significantly degrade intrinsic gain.

Why Output Resistance Matters in Circuit Design

The small-signal output resistance $r_o$ sets the upper limit for the intrinsic voltage gain ($A_v = g_m r_o$) of a single-stage common-source amplifier. Engineers use advanced DC sweep and AC analyses in Cadence to extract precise $g_{ds}$ values. Variations in temperature, biasing currents, and device sizing require iterative simulation runs to ensure robustness across process corners.

Frequently Asked Questions (FAQs)

Q: How does channel length affect $r_o$?
A: Increasing channel length ($L$) reduces channel length modulation effects, thereby increasing both Early voltage and output resistance.

Q: What is the impact of DIBL on output resistance?
A: Drain-Induced Barrier Lowering decreases $r_o$ at higher drain-source voltages because the drain potential assists in lowering the source potential barrier.