Example Data Table
| Stage | Gate | tPLH ns | tPHL ns | Wire ns | Load fF | Delay per fF | Fanout |
|---|---|---|---|---|---|---|---|
| Launch buffer | BUF | 0.07 | 0.07 | 0.03 | 8 | 0.004 | 2 |
| Decode NAND | NAND | 0.11 | 0.12 | 0.05 | 12 | 0.004 | 3 |
| Control XOR | XOR | 0.18 | 0.20 | 0.04 | 10 | 0.004 | 2 |
| Output MUX | MUX | 0.22 | 0.24 | 0.06 | 16 | 0.004 | 1 |
Formula Used
For each stage, the calculator selects a gate delay from tPLH, tPHL, average delay, worst delay, or traced transition delay.
Load delay = Load capacitance × Delay per fF
Fanout delay = Maximum of zero and Fanout minus one × Fanout penalty
Raw stage delay = Selected gate delay + Wire delay + Load delay + Fanout delay
Adjusted stage delay = Raw stage delay × PVT derate × Aging factor
Arrival time = Launch delay + Sum of adjusted stage delays
Required time = Clock period - Setup time - Clock skew - Uncertainty
Slack = Required time - Arrival time
How to Use This Calculator
- Select the delay mode that matches your timing study.
- Enter launch delay, clock period, setup time, skew, uncertainty, derate, and aging margin.
- Add every gate or path segment in correct signal order.
- Enter tPLH and tPHL values from a data sheet, library, or timing report.
- Add wire delay, load capacitance, load rate, fanout, and fanout penalty.
- Press Calculate Delay.
- Review adjusted delay, arrival time, required time, slack, and pass or fail status.
- Download CSV or PDF for reporting.
Understanding Logic Path Propagation Delay
What This Tool Measures
Propagation delay shows how long a signal needs to travel through a logic path. The path can include buffers, gates, multiplexers, clocked outputs, wires, and loads. This calculator models those parts as ordered stages. Each stage receives its own timing values. The tool then builds a complete path delay.
Why Stage Detail Matters
A simple gate count is rarely enough. One small gate can become slow when it drives heavy capacitance. A short wire can be harmless. A long route can dominate the path. Fanout also changes delay. More branches usually increase effective drive effort. This calculator separates those effects. That makes the final answer easier to inspect.
Rising and Falling Delays
Real gates often switch high and low at different speeds. The tPLH value describes a low to high output change. The tPHL value describes a high to low output change. Worst case mode uses the slower value. Trace mode follows signal polarity through inverting gates. That helps when a known input transition is important.
Derating and Margins
Silicon speed changes with process, voltage, and temperature. Aging can also reduce margin over time. The derate inputs add those practical effects. A path that passes without margin may fail after derating. The adjusted delay is therefore useful for conservative design checks.
Timing Closure View
The calculator also compares arrival time with required time. Arrival time starts with launch delay. It then adds the adjusted path delay. Required time subtracts setup time, skew, and uncertainty from the clock period. Positive slack means the path meets the target. Negative slack means the path needs improvement.
Design Use
Use this tool during early architecture, hand checks, lab estimates, and report review. Replace sample values with library or measurement data. Try different loads, buffers, and derates. The stage table can reveal the main delay contributor. That insight supports better sizing, placement, routing, and timing decisions.
FAQs
What is propagation delay in a logic circuit?
It is the time required for an input change to appear as an output change after passing through gates, wires, and loads.
What is the difference between tPLH and tPHL?
tPLH is delay for a low to high output change. tPHL is delay for a high to low output change.
When should I use worst case mode?
Use worst case mode when you need a conservative estimate and do not know the exact signal transition through every stage.
What does trace transition mode do?
It follows the selected input transition through inverting gates. It then chooses tPLH or tPHL based on each output transition.
Why include wire delay?
Wires add resistance and capacitance. In fast or large designs, routing delay can become as important as gate delay.
What does PVT derate mean?
It is a multiplier for process, voltage, and temperature variation. Higher values make the delay estimate more conservative.
What is slack?
Slack is required time minus arrival time. Positive slack passes the timing check. Negative slack means the path is late.
Can I use this for FPGA or ASIC paths?
Yes. Use timing values from the relevant FPGA report, ASIC library, data sheet, or measured lab result.