Calculator Input
Formula Used
The calculator estimates AOI22 output parasitic capacitance with these terms:
Cn_diff = Nn × (An × Cjn + Pn × Cjswn)
Cp_diff = Np × (Ap × Cjp + Pp × Cjswp)
Cdiff = Sharing factor × (Cn_diff + Cp_diff)
Coverlap = Miller factor × ((Wn_ov × Covn) + (Wp_ov × Covp))
Cwire = Wire length × Wire capacitance density
Cfanout = Fanout count × Input capacitance per gate
Ctotal = (Cdiff + Coverlap + Cwire + Cfanout + Cload + Cfringe) × Corner factor × Temperature factor
Q = Ctotal × VDD
Energy = 0.5 × Ctotal × VDD²
τ = Rdriver × Ctotal
Delay50 = 0.69 × τ
Power = Activity × Ctotal × VDD² × Frequency
How to Use This Calculator
Enter the AOI22 output node name and process note first.
Add the NMOS and PMOS output connected diffusion counts.
Enter area and perimeter values from layout or estimates.
Use junction and sidewall capacitance values from your process data.
Add overlap widths, route length, fanout, voltage, and driver resistance.
Press Calculate to display results above the form.
Use CSV or PDF export to save the calculated report.
Example Data Table
| Parameter | Example Value | Unit |
|---|---|---|
| NMOS output devices | 2 | count |
| PMOS output devices | 2 | count |
| NMOS area per device | 0.18 | µm² |
| PMOS area per device | 0.28 | µm² |
| Wire length | 25 | µm |
| Fanout | 3 | gates |
| Supply voltage | 0.80 | V |
| Driver resistance | 900 | Ω |
Understanding AOI22 Capacitance
An AOI22 gate combines two input AND paths and then inverts the OR result. Its output node often carries important parasitic capacitance. That capacitance comes from transistor diffusion, gate overlap, local metal, and driven input gates. A careful estimate helps timing checks before layout extraction is available.
Why This Estimate Matters
In digital design, extra capacitance slows switching. It increases the charge that the previous stage must move. It also raises dynamic energy. For an AOI22 cell, the output is connected to selected NMOS and PMOS drain regions. These regions add junction area and sidewall capacitance. The connected metal and fanout gates add more load.
What The Calculator Includes
This calculator separates the main contributors. NMOS diffusion capacitance is calculated from output connected area and perimeter. PMOS diffusion is treated the same way. Overlap capacitance is based on total output connected gate edge width. Wire capacitance is estimated from route length and capacitance per micron. Fanout capacitance uses the number of driven gates and their input capacitance.
Using Results In Design
The total capacitance is reported in femtofarads and picofarads. The tool also estimates output charge, switching energy, RC time constant, half swing delay, and dynamic power. These values are not a replacement for signoff extraction. They are useful for sizing, comparison, and early architecture work. A larger driver resistance or bigger fanout will increase delay quickly.
Model Limits
The model is compact and transparent. It assumes the user supplies effective dimensions for the output node. Layout sharing, contact effects, fringing fields, and stack internal nodes are simplified. Technology files may define capacitance differently. Use process values from your PDK when possible. For teaching or rough planning, typical values can still show clear trends.
Best Practice
Run several cases. Compare minimum, nominal, and maximum geometry values. Check the sensitivity to fanout and wire length. Then export the numbers for review. Keep each assumption documented, because parasitic estimates become more valuable when they can be traced and repeated.
For best accuracy, keep units consistent. Enter diffusion dimensions after any layout sharing assumption. Use a separate case for each output net. Small changes in wire length or fanout can dominate advanced nodes. Review exported data with timing notes later.
FAQs
What is AOI22 parasitic capacitance?
It is the unwanted capacitance at the AOI22 output node. It comes from diffusion regions, gate overlap, wiring, fanout gates, and layout effects.
Why does AOI22 output capacitance matter?
Higher capacitance slows the output transition. It also increases switching energy and dynamic power. This can affect timing closure and cell sizing.
Which AOI22 devices connect to the output?
Usually selected NMOS and PMOS drain regions connect to the output. The exact count depends on the transistor-level implementation and layout sharing.
Can this replace extracted layout capacitance?
No. It is an early estimate. Use extracted parasitics from layout tools for signoff timing, power, and reliability checks.
What unit is used for capacitance?
The calculator mainly uses femtofarads. It also converts total capacitance to picofarads for easier comparison with larger loads.
What is the diffusion sharing factor?
It adjusts the diffusion capacitance when layout sharing reduces or changes the effective output-connected diffusion area and perimeter.
What is the Miller factor?
It scales overlap capacitance when voltage movement across a coupled terminal increases or decreases the effective capacitive load.
Why include fanout capacitance?
The AOI22 output usually drives other gate inputs. Their input capacitance adds directly to the output load and affects delay.