Calculator Inputs
Example Data Table
| Method | Sample Inputs | Expected Result | Use Case |
|---|---|---|---|
| Timer input capture | Timer 72 MHz, PSC 71, delta 1000 ticks | 1000 Hz | PWM, tachometer, pulse sensor |
| Gate count | 1000 interrupts during 1000 ms, one edge per cycle | 1000 Hz | Simple ISR edge counter |
| CPU cycle delta | Core 72 MHz, 72000 cycles between interrupts | 1000 Hz | DWT timestamp debugging |
Formula Used
Timer tick rate: Timer tick rate = Timer clock / (Prescaler + 1)
Elapsed capture ticks: Total ticks = Capture delta + Overflow count × (ARR + 1)
Input capture frequency: Frequency = Signal cycles measured × Timer tick rate / Total ticks
Gate count frequency: Frequency = Interrupt count / (Gate time in seconds × Interrupts per signal cycle)
CPU cycle method: Frequency = Signal cycles measured × Core clock / CPU cycle delta
Interrupt load: CPU budget = Interrupt rate × ISR cycles / Core clock × 100
How to Use This Calculator
- Select the measurement method used in your firmware.
- Enter the real timer clock, not only the CPU clock.
- Add the timer prescaler register value exactly as configured.
- For capture mode, enter capture delta ticks and overflow count.
- For gate mode, enter the counted interrupts and gate time.
- For CPU cycle mode, enter core clock and cycle delta.
- Set interrupts per cycle to two when both edges trigger.
- Press calculate and review frequency, period, load, and uncertainty.
- Download CSV or PDF for records and lab reports.
Understanding interrupt frequency
Interrupt frequency measurement on STM32 boards is simple in concept, but small setup errors can create large mistakes. The timer clock, prescaler, auto reload value, and capture delta must match the running firmware. This calculator helps convert those register values into usable frequency, period, and interrupt load. It also works with a gate time method, where an interrupt counter is read after a fixed interval.
Why timer details matter
A timer does not always run at the same rate as the CPU core. Some STM32 families double the timer clock when an APB prescaler is used. Firmware should confirm the real timer input clock before using captured ticks. The prescaler then divides that clock by prescaler plus one. Each captured tick becomes a known time slice. A smaller prescaler improves resolution. A larger prescaler extends the measurable period before overflow.
Interrupt handler considerations
Counting edges inside an interrupt handler is useful for slow and medium signals. It is also easy to debug. However, very fast signals can overload the processor. Every interrupt consumes entry time, service time, and exit time. When the interrupt rate approaches a large share of CPU capacity, missed pulses can appear. Hardware input capture is usually better for higher frequencies, because the timer records edges even while code is busy.
Choosing a measurement method
Use input capture when you have two timestamp values from the same timer channel. Add overflow counts when the period crosses the auto reload boundary. Use gate counting when firmware increments a variable inside the handler during a known time window. Use cycle delta when DWT or another counter records cycles between repeated interrupts. For cleaner results, average several intervals and keep the signal source stable.
Interpreting the result
The calculated frequency is only as good as the timing source. Crystal tolerance, clock configuration, synchronization, interrupt jitter, and edge noise all affect accuracy. The uncertainty range shown here is an estimate for quick engineering review. It should not replace oscilloscope calibration. Still, it is helpful during firmware bring up, sensor validation, motor feedback testing, and lab reports. Exported CSV and PDF files keep the calculation easy to document. Always record firmware clock settings beside every captured dataset for traceability.
FAQs
1. What does this calculator measure?
It estimates signal frequency from interrupt counts, timer input capture ticks, or CPU cycle deltas. It also reports period, interrupt rate, timing resolution, uncertainty, and estimated processor load.
2. Which STM32 timer clock should I enter?
Enter the actual timer input clock after the clock tree is configured. Do not assume it always equals the core clock. Some APB timer clocks may be multiplied.
3. Why is prescaler entered as PSC value?
STM32 timers divide by prescaler plus one. If PSC is 71 and the timer clock is 72 MHz, the timer tick rate becomes 1 MHz.
4. When should I use overflow count?
Use overflow count when the timer wraps between two captured edges. Total ticks must include each full auto reload span plus the final capture delta.
5. What is interrupts per signal cycle?
It is the number of interrupt events produced by one full signal cycle. Use one for rising edges only. Use two when both rising and falling edges trigger.
6. Why is CPU budget important?
Every interrupt consumes processor cycles. A high interrupt rate can reduce available time for control loops, communication, and other tasks. High loads may cause missed events.
7. Is gate counting accurate for high frequency?
It can work, but the interrupt handler may become the limit. Hardware capture, timer encoder mode, external clock mode, or DMA may be safer for fast signals.
8. Can this replace an oscilloscope?
No. It is useful for firmware checks and calculations. For calibration, clock validation, jitter analysis, and noisy signals, compare results with proper lab instruments.