Calculator
This tool supports forward and inverse design: compute CL from C1/C2/Cs, or compute a missing capacitor to meet a target CL.
A common estimate is 1–5 pF, depending on package, layout, and IC input capacitance. Measure or simulate for best accuracy.
If your crystal specifies a load capacitance, select a mode that computes the missing capacitor to meet that target.
Formula used
The load capacitance seen by a crystal in a common Pierce oscillator model is approximated by:
Ceq = (C1 × C2) / (C1 + C2)CL = Ceq + CsHere, Cs is the total stray capacitance. It combines PCB, package, and input capacitances that appear in parallel with the series equivalent.
How to use this calculator
- Select a calculation mode based on what you know.
- Enter capacitor values and choose units for each field.
- Estimate or measure Cs (stray capacitance).
- If targeting datasheet CL, enter the target value.
- Click Calculate and review results above the form.
Example data table
| Scenario | C1 (pF) | C2 (pF) | Cs (pF) | Computed CL (pF) |
|---|---|---|---|---|
| Balanced network | 18 | 18 | 2 | 11 |
| Higher capacitors | 27 | 27 | 2 | 15.5 |
| Unbalanced network | 22 | 15 | 2 | 10.9 |
| More stray capacitance | 18 | 18 | 4 | 13 |
Values are illustrative. Always verify against your crystal and oscillator IC requirements.
Why load capacitance matters
Crystals meet their stated frequency only when they see a specified load capacitance (CL). In a Pierce oscillator, CL is set by two capacitors plus stray capacitance from pins, traces, and input capacitance. If CL is off, frequency shifts by parts‑per‑million (ppm).
Typical datasheet CL numbers
Common values are 6 pF, 9 pF, 12.5 pF, and 18 pF, usually paired with frequency tolerance in ppm. Small SMD parts may assume 1–3 pF stray; typical boards can be 2–5 pF or more. Design to the crystal’s stated CL rather than a generic default.
Pierce network relationship
With two capacitors to ground (C1, C2), the effective load is CL ≈ (C1·C2)/(C1+C2) + Cstray. If you choose C1=C2=C, then CL ≈ C/2 + Cstray, so C ≈ 2·(CL − Cstray). Balanced values are common and start reliably; unbalanced values help when one node has extra parasitics.
Estimating stray capacitance
Cstray includes pad capacitance, package effects, MCU/oscillator input capacitance, and PCB coupling. A practical first estimate is 2 pF for tight layouts and 3–5 pF for typical boards. If the MCU datasheet quotes an input capacitance, include it in Cstray. Short, symmetric traces and a solid ground return can materially reduce parasitics.
Designing for frequency accuracy
Higher CL usually lowers the oscillation frequency for parallel‑resonant crystals, but ppm per pF depends on pullability and motional parameters. Hit the specified CL first, then validate frequency error against your system budget. For trimming, change C1 and C2 symmetrically in small steps.
Component tolerances and temperature
Capacitor tolerance and dielectric behavior move CL. NP0/C0G parts are preferred for ppm accuracy; X7R/X5R can drop capacitance with DC bias and temperature, reducing CL. Crystal frequency also varies with temperature per its cut, so test across your range.
Startup margin and drive level
Too‑large capacitors can slow or prevent startup; too‑small values can increase sensitivity to parasitics and noise. Follow the oscillator IC’s recommended capacitor range and ESR limits. Respect the crystal’s maximum drive level to reduce aging and drift.
Validation and practical workflow
Workflow: estimate Cstray, compute C1/C2 for target CL, choose nearest standard values, then re‑calculate achieved CL. Prefer tighter‑tolerance parts where ppm matters, and avoid swapping dielectrics late in the design. After assembly, measure frequency at operating conditions and adjust in small steps if needed. Document CL assumptions for future PCB revisions.
Q: What is crystal load capacitance (CL)?
A: CL is the effective capacitance the crystal sees in the oscillator circuit. It is formed by the external capacitors and all parasitic capacitances. The crystal’s rated frequency assumes this specified CL.
Q: Why does Cstray matter so much?
A: When CL is small, a few picofarads of stray capacitance can be a large fraction of the target. Underestimating Cstray usually increases the achieved CL error and shifts frequency away from the nominal value.
Q: If I set C1 = C2, how do I pick their value quickly?
A: With equal capacitors, CL ≈ C/2 + Cstray, so C ≈ 2·(CL − Cstray). Choose the nearest standard capacitor value, then re-calculate the achieved CL to confirm.
Q: Should I always use NP0/C0G capacitors?
A: For ppm-level frequency accuracy, NP0/C0G is strongly preferred because it is stable with temperature and bias. For less critical clocks, X7R may work, but its capacitance can vary and change CL.
Q: What happens if the capacitors are too large?
A: Oversized capacitors load the amplifier more heavily, which can slow startup or stop oscillation. They also increase CL and typically pull the frequency lower. Stay within the oscillator IC’s recommended capacitor range.
Q: What happens if the capacitors are too small?
A: Very small capacitors can make the circuit more sensitive to parasitics and noise, and may shift CL low. Startup can improve, but frequency accuracy may suffer if Cstray dominates the total load.
Q: How can I verify the design after assembly?
A: Measure the oscillator frequency at the intended supply, temperature, and layout configuration. If the error is outside your budget, adjust C1 and C2 in small equal steps and re-test. Record the final values.
Notes for practical design
- Standard values: choose the nearest preferred capacitor series and re-check CL.
- Accuracy: oscillator input capacitance can shift CL significantly at low values.
- Layout matters: keep traces short and symmetric to reduce unwanted capacitance.
- Validation: measure frequency error if ppm-level accuracy is required.