Formula Used
Horizontal total = active width + front porch + sync width + back porch.
Vertical total = active height + front porch + sync width + back porch.
Pixel clock = horizontal total × vertical total × refresh rate ÷ 1,000,000.
TMDS clock estimate = pixel clock × deep color multiplier × chroma clock factor.
Encoded bandwidth = pixel clock × effective bits per pixel × encoding factor ÷ 1,000.
These formulas estimate display timing and link load. Device standards, firmware, and EDID limits may change final support.
How to Use This Calculator
Enter the active display width and height. Add horizontal and vertical blanking values from your timing source.
Set the refresh rate, color depth, chroma format, encoding method, and lane count.
Press Calculate to see the pixel clock, TMDS clock estimate, bandwidth, per-lane rate, and timing notes.
Use the CSV and PDF buttons to download the current calculation results.
Example Data Table
| Mode |
Total timing |
Refresh |
Chroma and depth |
Pixel clock |
Estimated encoded bandwidth |
| 1920 × 1080 |
2200 × 1125 |
60 Hz |
RGB 4:4:4, 8 bit |
148.500 MHz |
4.455 Gbps |
| 3840 × 2160 |
4400 × 2250 |
30 Hz |
RGB 4:4:4, 8 bit |
297.000 MHz |
8.910 Gbps |
| 3840 × 2160 |
4400 × 2250 |
60 Hz |
YCbCr 4:2:0, 8 bit |
594.000 MHz |
8.910 Gbps |
| 3840 × 2160 |
4400 × 2250 |
60 Hz |
RGB 4:4:4, 8 bit |
594.000 MHz |
17.820 Gbps |
Understanding HDMI Clock Frequency
HDMI video timing is more than active pixels. Each frame also includes blanking intervals. These intervals carry sync information and provide timing room. The clock frequency counts how many total pixel periods pass each second. A higher resolution, refresh rate, or blanking total raises the required clock.
Why the Pixel Clock Matters
The pixel clock is the base timing value for many HDMI modes. Displays and sources use it to keep each line and frame aligned. It also helps estimate data bandwidth. For standard RGB or 4:4:4 output, the TMDS clock usually follows the pixel clock at normal color depth. Deep color can raise the transmitted clock. Chroma subsampling can reduce the active data load.
Active Pixels and Blanking
Active width and height describe visible image pixels. Front porch, sync width, and back porch are not normally visible. They still count in the timing total. This is why two modes with the same visible resolution may need different clocks. Reduced blanking timings often lower the clock. Consumer television timings may use larger totals for compatibility.
Bandwidth Planning
A clock result alone does not show the full link load. Color depth, chroma format, encoding, and lane count affect bandwidth. This calculator estimates total encoded bandwidth and per-lane rate. It helps compare settings before choosing a cable, splitter, capture card, or display input. The result should be treated as a planning value. Device firmware may enforce stricter supported modes.
Practical Use
Start with the timing printed by your graphics tool, monitor manual, EDID reader, or video standard. Enter the active resolution and every blanking interval. Choose refresh rate, color depth, chroma format, lanes, and encoding. Then calculate. Review the pixel clock, TMDS clock estimate, and link bandwidth. If the mode exceeds a limit, try reduced blanking, lower refresh, lower depth, or 4:2:0 output. Recheck the result after every change. Stable links need timing support, cable margin, and device compatibility together.
Common Mistakes
Do not ignore porch values when copying a mode. Do not use only visible pixels for high refresh calculations. Also avoid mixing pixel clock and total bandwidth. They describe related but different limits. When unsure, compare both values with the published input specification for safe planning.
FAQs
What is HDMI clock frequency?
It is the timing rate used to send pixel periods through an HDMI video mode. It depends on active resolution, blanking totals, and refresh rate.
Is pixel clock the same as TMDS clock?
For many 8-bit 4:4:4 modes, they are often the same. Deep color and some chroma formats can change the transmitted clock estimate.
Why do blanking intervals matter?
Blanking intervals are part of the full video timing. The source must clock through those periods, even though they are not visible pixels.
Can this calculator check cable support?
It estimates clock and bandwidth needs. Cable quality, device ports, firmware, and display EDID support still decide whether a mode works reliably.
What does 4:2:0 change?
YCbCr 4:2:0 reduces chroma data. It can lower bandwidth and may reduce the transmitted clock estimate for compatible HDMI modes.
Why is 4K 60 Hz demanding?
It combines high pixel count with a high refresh rate. With 4:4:4 color, the encoded bandwidth can approach the 18 Gbps class.
Should I use reduced blanking?
Reduced blanking can lower the pixel clock. Use it only when the source and display both support the timing mode.
Does FRL use the same clock idea?
FRL uses a different link structure than classic TMDS. This tool still gives a useful bandwidth estimate when FRL encoding is selected.