Online Frequency Synthesizer Calculator

Frequency Synthesizer Inputs

Calculator mode

Reference or clock frequency

Reference unit

Target output frequency

Target unit

PLL reference divider R

PLL integer divider N

PLL fractional numerator

PLL fractional modulus

PLL output divider

DDS accumulator bits

DDS tuning word

Example Data Table

Use case	Reference	Settings	Expected result
Fractional PLL radio local oscillator	10 MHz	R = 1, N = 120, numerator = 25, modulus = 100, D = 2	601.25 MHz output
Integer PLL clock source	25 MHz	R = 5, N = 200, numerator = 0, modulus = 1, D = 4	250 MHz output
DDS firmware tuning	100 MHz clock	32-bit accumulator, tuning word 429496730	About 10 MHz output

Formula Used

PLL phase detector: Fpfd = Fref / R.

PLL feedback ratio: Ratio = N + numerator / modulus.

PLL VCO frequency: Fvco = Fpfd × Ratio.

PLL output: Fout = Fvco / output divider.

Fractional PLL step: Step = Fpfd / (modulus × output divider).

DDS output: Fout = tuning word × clock / 2^{accumulator bits}.

DDS resolution: Resolution = clock / 2^{accumulator bits}.

Error: Error = calculated output − target output.

PPM error: PPM = Error / target output × 1,000,000.

Angular frequency: ω = 2πf.

How to Use This Calculator

Select PLL mode for divider based circuits, or DDS mode for tuning word based circuits.
Enter the stable reference frequency or clock frequency with the correct unit.
Enter the target output frequency for error and suggested setting checks.
For PLL work, enter R, N, numerator, modulus, and output divider values.
For DDS work, enter accumulator bits and the current tuning word.
Press Calculate to show results above the form.
Use CSV or PDF export to save the calculation record.

Frequency Synthesizer Planning Guide

A frequency synthesizer creates precise output signals from a stable reference. It is used in radios, test benches, clocks, radar, and measurement tools. The main goal is simple. You choose a reference. You choose dividers. Then the circuit produces a controlled output.

Why Divider Choices Matter

Divider choices set the available channel spacing. In a PLL design, the phase detector frequency is the reference divided by R. The feedback ratio then multiplies that detector rate. Integer designs use whole ratios. Fractional designs add a numerator and modulus. That fractional part gives smaller steps. It also adds spurs, so clean planning matters.

VCO and Output Limits

The voltage controlled oscillator often runs higher than the final signal. An output divider then brings the signal down. This approach can improve usable coverage. It also helps match synthesizer chips that need a certain VCO range. Always compare the calculated VCO with the device data sheet. A correct output is not enough. The internal oscillator must also stay inside limits.

DDS Mode

A direct digital synthesizer uses a tuning word. The word selects a fraction of the clock frequency. More accumulator bits give finer resolution. A higher clock gives wider range, but it also raises design demands. The calculator estimates the tuning word and the expected error. That helps when firmware must load register values.

Error and Resolution

Frequency error shows the difference from the target. The ppm value makes comparison easier at different bands. A few hertz can be important at low channels. The same error may be tiny at microwave ranges. Step size shows the smallest theoretical move for the entered settings. Real hardware can still have limits from loop filters, charge pumps, clocks, and reference quality.

Practical Workflow

Start with the required output. Enter the known reference. Pick a divider that keeps the detector frequency practical. Then choose the modulus or accumulator size. Check the suggested ratio or tuning word. Export the result before testing hardware. Keep records for each band plan. Clear notes reduce register mistakes. They also make later debugging faster.

For shared teams, document assumptions clearly. Record units, rounding rules, device limits, and measured results. This habit protects production tuning work during final validation.

FAQs

What does this frequency synthesizer calculator do?

It calculates PLL and DDS output frequency, step size, target error, ppm error, period, and angular frequency. It also suggests close divider or tuning word values for a target frequency.

What is the PLL reference divider?

The reference divider reduces the reference signal before the phase detector. A larger divider lowers detector frequency. That can change channel spacing, lock behavior, and loop design choices.

What is fractional modulus?

The modulus is the denominator of the fractional divider. A larger modulus can give finer frequency resolution. It may also affect spur planning and register limits.

Why is VCO frequency shown?

Many synthesizer chips generate a higher internal VCO frequency first. The output divider then reduces it. Checking VCO frequency helps confirm the selected settings fit the hardware range.

How is ppm error useful?

PPM error expresses frequency error relative to the target. It helps compare accuracy across low, high, and microwave frequencies using the same scale.

Can this tool calculate DDS tuning words?

Yes. Select DDS mode. Enter the clock frequency, accumulator bits, tuning word, and target frequency. The result includes output frequency, resolution, and a suggested tuning word.

Does the calculator include phase noise?

No. It focuses on frequency planning. Phase noise depends on device architecture, loop bandwidth, reference quality, charge pump settings, power design, and board layout.

Are the exported files based on current inputs?

Yes. Press Download CSV or Download PDF after entering your values. The file contains the same calculated fields shown in the result table.