PCB Trace Width Calculator

Example Data Table

Examples are illustrative. Manufacturing limits and airflow can change results.

Formula Used

This calculator uses the IPC-2221 empirical relationship between current, allowable temperature rise, and conductor cross-sectional area:

I = k × (ΔT)0.44 × A0.725

Where I is current in amperes, ΔT is allowed temperature rise in °C, A is cross-sectional area in mil², and k depends on layer placement. External layers use a larger k value than internal layers.

After solving for A, trace width is computed as: Width = A / Thickness with thickness in mils. If length is enabled, resistance is estimated using R = ρ × L / (w × t), then voltage drop V = I × R and power P = I² × R.

How to Use This Calculator

1. Enter the maximum continuous current your trace must carry.
2. Choose an allowable temperature rise for your reliability target.
3. Select internal or external layer to match your routing layer.
4. Set copper thickness using oz, µm, or mil inputs.
5. Pick an output unit and press Calculate.
6. Optional: enable length to estimate resistance and voltage drop.
7. Use the download buttons to export a CSV or PDF report.

Design tip: keep extra margin for connectors, vias, and hotspots.

Notes and Limits

• These equations are empirical and best for initial sizing.
• High-frequency traces require impedance and skin-effect design.
• Plated copper, solder mask, airflow, and board stack-up matter.
• Always check your fabricator’s minimum trace/space rules.

Design Context for Trace Width

Trace width is a thermal and electrical choice. A wider conductor lowers resistance, reduces heating, and improves robustness during assembly. Many boards start with 1 oz copper (about 35 µm) and then adjust widths based on current, layer placement, and allowable temperature rise. As a reference, 1 A on an external 1 oz trace with a 10 °C rise often falls near 10–15 mil.

Why Internal Traces Need More Margin

Internal layers are surrounded by dielectric, so heat escapes slower than on an outer layer exposed to air. This is why the calculator uses a smaller IPC coefficient for internal routing. For the same current and ΔT, internal traces typically require noticeably more cross‑sectional area.

Typical Temperature Rise Targets

Professional layouts often target a 10–20 °C rise for continuous loads, especially near regulators, connectors, and motor drivers. Higher rises can be acceptable for short duty cycles, but they increase copper resistance and can stress solder joints over time.

Copper Thickness and Practical Options

Copper thickness changes width requirements directly. Doubling from 1 oz to 2 oz roughly halves the width needed for the same cross‑sectional area. Heavy copper (3–4 oz) is common in power electronics, while fine signal boards may use thinner copper for tighter routing.

Voltage Drop and Power Loss Checks

When you enable length, the calculator estimates resistance using copper resistivity and an average temperature. This allows quick checks of voltage drop and I²R loss. For example, at a few amperes, long thin traces can waste significant power and shift supply rails.

Interpreting the Results for Routing

Treat the reported width as a baseline. Add clearance for manufacturing, thermal hotspots, and neck‑downs near pads. If the width exceeds routing space, consider heavier copper, multiple parallel traces, or dedicated copper pours tied with stitching vias.

Data Points That Often Influence Width

Key inputs are current, ΔT, copper thickness, and layer type. Typical hobby fabrication supports 6–8 mil minimum trace/space, while many professional shops comfortably produce 4 mil or less. Power paths near connectors often use widths above 40–80 mil, depending on current and copper weight.

Best Practice Workflow

Start with your maximum continuous current and a conservative ΔT. Calculate the width, then validate against board constraints. Re‑run with heavier copper or lower rise if needed. Finally, review the voltage drop result for long runs and document exports in your design notes.

FAQs

1) Which standard does this calculator follow?

It uses the IPC‑2221 empirical current-to-area relationship. It is useful for early sizing and comparisons, but final designs should consider stack‑up, airflow, and fabrication constraints.

2) Is this valid for AC or high-frequency signals?

It is intended for thermal sizing with steady current. High-frequency traces also require impedance control, skin effect, and return-path planning, which can dominate geometry decisions.

3) What temperature rise should I choose?

Many designers pick 10–20 °C for continuous power traces. Use lower rise for reliability, hot enclosures, or sensitive components, and higher rise only when duty cycle is limited.

4) Does solder mask affect the width requirement?

Yes. Solder mask can slightly reduce convective cooling on outer layers. Treat results as a baseline and add margin when traces are masked, bundled, or near heat sources.

5) How accurate are the resistance and drop estimates?

They are first-order estimates using copper resistivity and an average temperature. Real results vary with plating, surface finish, and local heating, but the estimates are helpful for quick checks.

6) What if the required width is too large?

Increase copper thickness, use wider pours, route parallel traces, shorten the run, or move power closer to the load. Stitching vias can also share current between layers.

7) Should I include vias and connectors in sizing?

Yes. Vias and connectors often become the limiting points. Use multiple vias for higher current, check connector ratings, and keep neck‑downs short. Validate with thermal testing for critical paths.