CMOS Inverter Delay Calculator

Calculator Inputs

Supply voltage VDD (V)

Typical: 0.8–1.8 V, depending on process.

NMOS threshold Vth,n (V)

PMOS threshold Vth,p (V)

Enter negative or magnitude; magnitude is used.

NMOS width Wn (µm)

NMOS length Ln (µm)

PMOS width Wp (µm)

Often Wp ≈ 2×Wn to balance delays.

PMOS length Lp (µm)

βn = μn·Cox (A/V²)

Higher β lowers RN and speeds tpHL.

βp = μp·Cox (A/V²)

Lower β increases RP and slows tpLH.

Gate load per fanout (fF)

Diffusion load per fanout (fF)

Wire capacitance (fF)

Extra lumped load (fF)

Add pad, probe, or routing lumped capacitance.

Fanout (number of identical loads)

Fanout scales the (gate + diffusion) portion.

Process corner FastTypicalSlow

Corner affects effective resistance.

Temperature (°C)

Higher temperature increases delay in this model.

Input transition (ps)

Used only if slew penalty is enabled.

Slew penalty OnOff

Adds a fraction of input slew to delay.

Calculate Delay Reset

Example Data Table

Use these sample values to verify outputs and compare corners.

Formula Used

The calculator models the inverter as a first-order RC network. It estimates an equivalent on-resistance for NMOS and PMOS, then applies a 0.69RC propagation delay.

• Rn,eq ≈ 1 / (βn · (W/L)n · (VDD − Vth,n))
• Rp,eq ≈ 1 / (βp · (W/L)p · (VDD − |Vth,p|))
• CL,total = fanout·(Cgate + Cdiff) + Cwire + Cextra
• tpHL ≈ 0.69 · Rn,eq · CL,total
• tpLH ≈ 0.69 · Rp,eq · CL,total

Optional slew penalty adds a small fraction of input transition to each delay, and the corner and temperature settings scale the effective resistance for quick what‑if analysis.

How to Use This Calculator

1. Enter VDD and threshold values for your technology.
2. Set W/L for NMOS and PMOS based on sizing targets.
3. Describe the load using fanout, gate, diffusion, and wiring capacitances.
4. Select a corner and temperature to approximate PVT impact.
5. Click Calculate Delay to see results above the form.
6. Use the download buttons to export the latest calculation.

FAQs

1) What do tpHL and tpLH mean?

tpHL is the high-to-low output propagation delay during discharge. tpLH is the low-to-high delay during charge. Different strengths of NMOS and PMOS make them unequal.

2) Why does the calculator use 0.69RC?

0.69RC approximates the time for a first-order RC node to reach 50% of a step response. It is a common engineering estimate for inverter delay under simplified conditions.

3) How should I choose βn and βp?

Use values from your PDK, characterization, or textbook references. β represents μ·Cox and varies with process and bias. If unsure, start with typical values and tune using measured delays.

4) Why is PMOS usually wider?

Hole mobility is typically lower than electron mobility, making PMOS weaker. Increasing PMOS width raises (W/L)p, reduces Rp, and helps balance tpLH with tpHL.

5) What capacitances matter most for delay?

Total load capacitance dominates. Fanout multiplies gate and diffusion components, while wire capacitance grows with routing length. Extra load accounts for pads, probes, and other lumped effects.

6) What does the corner setting change?

The corner applies a simple resistance multiplier: fast reduces resistance, slow increases it. It is not a full PVT model, but it helps explore sensitivity and compare scenarios quickly.

7) How is temperature handled?

The model scales resistance using a power law based on absolute temperature. Higher temperatures increase resistance and delay. Real silicon can be more complex, so treat results as an estimate.

8) Is fmax an exact maximum frequency?

No. fmax here is a rough reciprocal of the sum of rise and fall delays for a toggling output. Real limits also depend on noise margins, duty cycle, loading variability, and upstream slew.